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preliminary information amd duron processor data sheet publication # 23802 rev: e issue date: september 2000 tm
preliminary information trademarks amd, the amd logo, amd duron, and combinations thereof, and 3dnow! are trademarks of advanced micro devices, inc. mmx is a trademark of intel corporation. digital and alpha are trademarks of digital equipment corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2000 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
contents iii 23802e?september 2000 amd duron? processor data sheet preliminary information contents contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 amd duron ? processor microarchitecture summary . . . . . 2 2 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 signaling technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 push-pull (pp) drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 amd system bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 full-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 stop grant and sleep states. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 probe state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 connection and disconnection protocol . . . . . . . . . . . . . . . . 11 connection protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 connection state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 amd duron processor interface signal groupings . . . . . . . 19 6.3 voltage identification (vid[4:0]) . . . . . . . . . . . . . . . . . . . . . . 20 6.4 frequency identification (fid[3:0]) . . . . . . . . . . . . . . . . . . . . 20 6.5 vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . 21 6.6 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.9 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.10 sysclk and sysclk# dc and ac characteristics . . . . . . 22 6.11 amd system bus pins ac and dc characteristics . . . . . . . . 25 6.12 amd system bus ac characteristics . . . . . . . . . . . . . . . . . . . 26 6.13 general ac and dc characteristics . . . . . . . . . . . . . . . . . . . . 27 6.14 apic pins ac and dc characteristics . . . . . . . . . . . . . . . . . . 28
iv contents amd duron ? processor data sheet 23802e ? september 2000 preliminary information 7 signal and power-up requirements . . . . . . . . . . . . . . . . . . . . .31 7.1 power-up requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 signal sequence and timing description . . . . . . . . . . . . . . . 31 clock multiplier selection (fid[3:0]). . . . . . . . . . . . . . . . . . . 34 7.2 processor warm reset requirements . . . . . . . . . . . . . . . . . . 36 the amd duron ? processor and northbridge reset pins . 36 8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.3 socket tabs for heatsink clips . . . . . . . . . . . . . . . . . . . . . . . 39 9 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 detailed pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 a20m# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 amd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 amd system bus pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 analog pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 clkfwdrst pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 clkin, rstclk (sysclk) pins . . . . . . . . . . . . . . . . . . . . . . 57 connect pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 corefb and corefb# pins . . . . . . . . . . . . . . . . . . . . . . . . . 57 dbrdy and dbreq# pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ferr pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 fid[3:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 flush# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ignne# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 init# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 intr pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 k7clkout and k7clkout# pins . . . . . . . . . . . . . . . . . . . . 59 key pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 nc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 nmi pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 pga orientation pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 pll bypass and test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 pwrok pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 saddin[1]# and saddout[1:0]# pins . . . . . . . . . . . . . . . . . 60 scan pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
contents v 23802e ? september 2000 amd duron ? processor data sheet preliminary information scheck[7:0]# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 smi# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 stpclk# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysclk and sysclk# pins . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysvrefmode pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 vcca pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 vid[4:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 vrefsys pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 zn, vcc_z, zp, and vss_z pins . . . . . . . . . . . . . . . . . . . . . . . 62 10 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 standard amd duron ? processor products . . . . . . . . . . . . . . . . . . . 65 appendix a conventions, abbreviations, and references . . . . . . . . . . . . . . . . . . . . 67 signals and bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 data terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 abbreviations and acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
vi contents amd duron ? processor data sheet 23802e ? september 2000 preliminary information
list of figures vii 23802e ? september 2000 amd duron ? processor data sheet preliminary information list of figures figure 1. typical amd duron ? processor system block diagram . . . . . 3 figure 2. logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. amd duron processor power management states. . . . . . . . . . . 9 figure 4. example system bus disconnection sequence . . . . . . . . . . . . . 13 figure 5. exiting stop grant state/bus reconnection sequence . . . . . . 14 figure 6. system connection states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. processor connection states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. sysclk and sysclk# differential clock signals . . . . . . . . . 23 figure 9. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. signal relationship requirements during power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. typical sip protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. pga package, top, side, and bottom views . . . . . . . . . . . . . . . 38 figure 13. socket a with outline of socket and heatsink tab . . . . . . . . . 39 figure 14. socket a heatsink tab side view . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15. amd duron processor pin diagram ? topside view . . . . . . . . 42 figure 16. pga opn example for the amd duron processor. . . . . . . . . . 65
viii list of figures amd duron ? processor data sheet 23802e ? september 2000 preliminary information
list of tables ix 23802e ? september 2000 amd duron ? processor data sheet preliminary information list of tables table 1. amd duron ? processor power management states . . . . . . . . 12 table 2. thermal design power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. amd duron processor interface signal groupings . . . . . . . . . 19 table 4. vid[4:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. fid[3:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. vcc_core voltage and current. . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. sysclk and sysclk# dc characteristics . . . . . . . . . . . . . . . 23 table 11. sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . . 23 table 12. amd system bus pins dc characteristics . . . . . . . . . . . . . . . . 25 table 13. amd system bus ac characteristics . . . . . . . . . . . . . . . . . . . . . 26 table 14. general ac and dc characteristics. . . . . . . . . . . . . . . . . . . . . . 27 table 15. apic pins ac and dc characteristics . . . . . . . . . . . . . . . . . . . . 28 table 16. sip protocol states and actions . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. reset# minimum duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. pin name abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. socket a pin cross-reference by pin location . . . . . . . . . . . . 49 table 20. fid[3:0] clock multiplier encodings . . . . . . . . . . . . . . . . . . . . . 58 table 21. vid[4:0] code to voltage definition . . . . . . . . . . . . . . . . . . . . . 62 table 22. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 23. acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
x list of tables amd duron ? processor data sheet 23802e ? september 2000 preliminary information
revision history xi 23802e ? september 2000 amd duron ? processor data sheet preliminary information revision history date rev description september 2000 e revised table 2, ?thermal design power,? on page 17 revised table 9, ?vcc_core voltage and current,? on page 23 revised opn to include the new 750mhz speed grade in chapter 10, ?ordering information? on page 65 september 2000 d added information about the 750 mhz amd duron? processor as follows: table 2, ?thermal design power,? on page 17 table 7, ?operating ranges,? on page 21 table 9, ?vcc_core voltage and current,? on page 22 august 2000 c added table 2, ?thermal design power,? on page 17 revised vcc_core to 1.6 in table 7, ?operating ranges,? on page 24 revised and reorganized the ac and dc characteristics for sysclk and sysclk#. see table 11, ?sysclk and sysclk# ac characteristics,? on page 27, and table 10, ?sysclk and sysclk# dc characteristics,? on page 26 added table 15, ?miscellaneous pins ac and dc characteristics? on page 30 revised mechanical drawings in chapter 8, pages 38 - 40 made corrections and updates to chapter 9, ?pin descriptions?, in particular table 19, ?socket a pin cross-reference by pin location,? on page 51 revised opn from 4 digits to 3 (i.e. from 0 550=0550 mhz to 550 mhz) in chapter 10, ?ordering information? on page 65 june 2000 b initial public release
xii revision history amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 1 overview 1 23802e ? september 2000 amd duron ? processor data sheet preliminary information 1 overview the amd duron? processor enables an optimized pc solution for value-conscious business and home users by providing the capability and flexibility to meet their computing needs for both today and tomorrow. the amd duron processor is the latest offering from amd designed for the value segment of the market. the innovative design was developed to accommodate new and more advanced applications, meeting the requirements of today ? s most demanding value-conscious buyers without compromising their budget. delivered in a pga package, the amd duron processor is the new amd workhorse processor for value desktop systems, delivering the highest integer, floating-point and 3d multimedia performance for applications running on x86 system platforms. the amd duron processor provides value-conscious customers with access to advanced technology that allows their system investment to last for years to come. the amd duron processor is designed as a solid platform for surfing the internet, digital entertainment, and personal creativity. in addition, it is engineered to enable superior business productivity by delivering an optimized combination of computing performance and value. the amd duron processor features the seventh-generation microarchitecture with an integrated l2 cache, which supports the growing processor and system bandwidth requirements of emerging software, graphics, i/o, and memory technologies. the amd duron processor ? s high-speed execution core includes multiple x86 instruction decoders, a dual-ported 128-kbyte split level-one (l1) cache, a 64-kbyte on-chip l2 cache, three independent integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of-order, three-way floating-point engine. the floating-point engine is capable of delivering superior performance on numerically complex applications. the amd duron processor microarchitecture incorporates enhanced 3dnow! ? technology, a high-performance cache architecture, and the 200-mhz 1.6-gigabyte per second
2 overview chapter 1 amd duron ? processor data sheet 23802e ? september 2000 preliminary information amd system bus. the amd system bus combines the latest technological advances, such as point-to-point topology, source-synchronous packet-based transfers, and low-voltage signaling, to provide the most powerful, scalable bus available for any x86 processor. the amd duron processor is binary-compatible with existing x86 software and backwards compatible with applications optimized for mmx ? and 3dnow! instructions. using a data format and single-instruction multiple-data (simd) operations based on the mmx instruction model, the amd duron processor can produce as many as four, 32-bit, single-precision floating-point results per clock cycle. the enhanced 3dnow! technology implemented in the amd duron processor includes new integer multimedia instructions and software-directed data movement instructions to deliver a superior performance to celeron in multimedia and number-intensive applications. 1.1 amd duron ? processor microarchitecture summary the following features summarize the amd duron processor microarchitecture: the industry ? s first nine-issue, superpipelined, superscalar x86 processor microarchitecture designed for high clock frequencies multiple x86 instruction decoders three out-of-order, superscalar, fully pipelined floating-point execution units, which execute all x87 (floating-point), mmx and 3dnow! instructions three out-of-order, superscalar, pipelined integer units three out-of-order, superscalar, pipelined address calculation units 72-entry instruction control unit advanced dynamic branch prediction enhanced 3dnow! technology with new instructions to enable improved integer math calculations for speech or video encoding and improved data movement for internet plug-ins and other streaming applications 200-mhz amd system bus (scalable beyond 400 mhz) enabling leading-edge system bandwidth for data movement-intensive applications
chapter 1 overview 3 23802e ? september 2000 amd duron ? processor data sheet preliminary information high-performance cache architecture featuring an integrated 128-kbyte l1 cache and a 16-way, on-chip 64-kbyte l2 cache the amd duron processor delivers superior system performance in a cost-effective, industry-standard form factor. the amd duron processor is compatible with motherboards based on amd ? s socket a. figure 1 on page 3 shows a typical amd duron processor system block diagram. figure 1. typical amd duron? processor system block diagram dram agp bus memory bus agp pci bus lan scsi system management bios isa bus usb dual eide amd duron ? processor system controller (northbridge) peripheral bus controller (southbridge)
4 overview chapter 1 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 2 interface signals 5 23802e ? september 2000 amd duron ? processor data sheet preliminary information 2 interface signals 2.1 overview the amd system bus architecture is designed to deliver superior data movement bandwidth for value x86 platforms. the system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 72-bit bidirectional data channel, including 8-bit error code correction [ecc] protection), source-synchronous clocking, and a packet-based protocol. in addition, the system bus supports several control, clock, and legacy signals. the interface signals use an impedance controlled push-pull low-voltage swing signaling technology contained within the socket a mechanical connector, which is mechanically compatible with the industry-standard sc242 connector. for more information, see ? amd system bus signals ? on page 6, chapter 9, ? pin descriptions ? on page 41, and the amd system bus specification , order# 21902. 2.2 signaling technology the amd system bus uses a low-voltage, swing signaling technology, which has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. the signals are push-pull and impedance compensated. the signal inputs use differential receivers, which require a reference voltage (v ref ). the reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. termination resistors are not needed because the driver is impedance matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold. for more information about pins and signals, see chapter 9, ? pin descriptions ? on page 41.
6 interface signals chapter 2 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 2.3 push-pull (pp) drivers the socket a amd duron ? processor supports push-pull (pp) drivers. the system logic configures the amd duron processor with the configuration parameter called syspushpull (1=pp). the impedance of the pp drivers is set to match the impedance of the motherboard by two external resistors connected to the zn and zp pins. see ? zn, vcc_z, zp, and vss_z pins ? on page 62 for more information. 2.4 amd system bus signals the amd system bus is a clock-forwarded, point-to-point interface with the following three point-to-point channels: a 13-bit unidirectional output address/command channel a 13-bit unidirectional input address/command channel 72-bit bidirectional data channel for more information, see chapter 6, ? electrical data ? on page 19 and the amd system bus specification , order# 21902.
chapter 3 logic symbol diagram 7 23802e ? september 2000 amd duron ? processor data sheet preliminary information 3 logic symbol diagram figure 2. logic symbol diagram picclk picd[1:0]# apic sdata[63:0]# sdatainclk[3:0]# sdataoutclk[3:0]# scheck[7:0]# data saddin[14:1]# saddinclk# probe/syscmd saddout[14:0]# saddoutclk# vid[3:0] fid[3:0] a20m# clkfwdrst connect corefb corefb# ferr ignne# init# intr nmi procrdy pwrok reset# sfillval# smi# stpclk# sysclk# sysclk clock voltage control frequency control legacy request amd duron ? processor sdatainval# sdataoutval# power and initialization management
8 logic symbol diagram chapter 3 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 4 power management 9 23802e ? september 2000 amd duron ? processor data sheet preliminary information 4 power management 4.1 power management states the amd duron ? processor uses multiple advanced power states to place the processor in reduced power modes. these power states are used to enhance processor performance, minimize power dissipation, and provide a balance between performance and power (see ? power dissipation ? on page 22 for more information). in addition, these power states conform to the industry-standard advanced configuration and power interface (acpi) requirements for processor power states. (acpi is a specification for system hardware and software to support os-oriented power management.) each state has a specific mechanism that allows the processor to enter the respective state. figure 3 shows the power management states of the amd duron processor. the figure includes the acpi power states for the processor, labeled as cx. figure 3. amd duron ? processor power management states c1 auto halt c0 normal / full-on execute hlt and special cycle smi#, intr, nmi, init#, reset# incoming probe p r o b e s e r v i c e d stpclk# asserted s t p c l k # a s s e r t e d s t p c l k # d e a s s e r t e d c2 stop grant incoming probe probe serviced probe state stpclk# deasserted read plvl2 register c3 sleep s t p c l k # a s s e r t e d s t p c l k # d e a s s e r t e d r e a d p l v l 3 r e g i s t e r legend: hardware transitions software transitions note * note: the c1 to c2 transition by way of the stpclk# assertion/deassertion is not defined for acpi-compliant systems.
10 power management chapter 4 amd duron ? processor data sheet 23802e ? september 2000 preliminary information the following sections describe each of the low-power states. note: in all power management states, the system must not disable the system clock (sysclk/sysclk#) to the processor. full-on the full-on or normal state refers to the default power state and means that all functional units are operating at full processor clock speed. halt state when the amd duron processor executes the hlt instruction, the processor issues a halt special cycle to the system bus. the phase-lock loop (pll) continues to run, enabling the processor to monitor bus activity and provide a quick resume from the halt state. the processor may enter a lower power state. the halt state is exited when the processor samples init#, intr (if interrupts are enabled), nmi, reset#, or smi#. stop grant and sleep states after recognizing the assertion of stpclk#, the amd duron processor completes all pending and in-progress bus cycles and acknowledges the stpclk# assertion by issuing a stop grant special bus cycle to the system bus. the processor may enter a lower power state. from a software standpoint, the sleep/stop grant state is entered by reading the plvl registers located in an acpi-compliant peripheral bus controller. the difference between the stop grant state and the sleep state is determined by which plvl register software reads from the peripheral bus controller. if the software reads the plvl_2 register, the processor enters the stop grant state. in this state, probes are allowed, as shown in figure 3 on page 9. if the software reads the plvl_3 register, the processor enters the sleep state, where probes are not allowed. this action is accomplished by disabling snoops within an acpi-compliant system controller. the sleep/stop grant state is exited upon the deassertion of stpclk# or the assertion of reset#. after the processor enters the full-on state, it resumes execution at the instruction boundary where stpclk# was initially recognized. the processor latches init#, intr (if interrupts are enabled), nmi, and smi#, if they are asserted during the stop grant or sleep state. however, the processor does not exit this state until the deassertion of stpclk#. when stpclk# is deasserted,
chapter 4 power management 11 23802e ? september 2000 amd duron ? processor data sheet preliminary information any pending interrupts are recognized after returning to the normal state. if reset# is sampled asserted during the stop grant or sleep state, the processor immediately returns to the full-on state and the reset process begins. probe state the probe state is entered when the system requires the processor to service a probe. when in the probe state, the processor responds to a probe cycle in the same manner as when it is in the full-on state. when the probe has been serviced, the processor returns to the same state as when it entered the probe state. 4.2 connection and disconnection protocol the amd duron processor enhances power savings in each of the power management states when the system logic disconnects the processor from the system bus and slows down the internal clocks. entering the lowest power state is accomplished with a connection protocol between the processor and system logic. the system can initiate a bus disconnection upon the receipt of a stop grant special cycle. if required by the system, the processor disconnects from the system bus and slows down its internal clocks before entering the stop grant or sleep state. if the system requires the processor to service a probe while it is in the stop grant state, it must first request that the processor increase its clocks to full speed and reconnect to the system bus. table 1 on page 12 describes the amd duron processor power states using the connection protocol as described on page 12. amd system bus connections and disconnections are controlled by an enable bit within the system controller.
12 power management chapter 4 amd duron ? processor data sheet 23802e ? september 2000 preliminary information connection protocol in addition to the legacy stpclk# signal and the halt and stop grant special cycles, the amd system bus connection protocol includes the connect, procrdy, and clkfwdrst signals and a connect special cycle. amd system bus disconnects are initiated by the system controller in response to the receipt of a stop grant special cycle. reconnections are initiated by the processor in response to an interrupt or stpclk# deassertion, or by the system to service a probe. a disconnect request is implicit, if enabled, in the processor stop grant special cycle request. it is expected that the system table 1. amd duron ? processor power management states state name entered exited full-on / normal this is the full-on running state of the processor initiates either a halt instruction or stpclk# assertion. halt execution of the halt instruction. a special cycle is issued. the processor may enter a lower power state. the processor exits and returns to the run state upon the occurrence of init#, intr, nmi, smi# or reset#. the processor transitions to the stop grant state if stpclk# is asserted and returns to the halt state upon stpclk# deassertion. stop grant the processor transitions to the stop grant state with the assertion of stpclk# (as a result of a read to the plvl_2 register). a stop grant special cycle is issued. the processor may enter a lower power state. note: while in this state, interrupts are latched and serviced when the processor transitions to the full-on state. the processor transitions to the full-on or halt state upon stpclk# deassertion. reset# asserted initializes the processor but, if stpclk# is asserted, the processor returns to the stop grant state. probe a transition to the probe state occurs when the system asserts connect. the processor remains in this state until the probe is serviced and any data is transferred. the processor returns to the halt or stop grant state when the probe has been serviced and the system deasserts connect. if the processor was disconnected from the bus in the previous state, bus disconnection occurs and the internal frequency of the processor is again slowed down. sleep the processor can enter its lowest power state, sleep, from the full-on state with the assertion of stpclk# (as a result of a read to the plvl_3 register). note: while in this state, interrupts are latched and serviced when the processor transitions to the full-on state. the processor transitions to the run state upon stpclk# deassertion. asserting reset# initializes the processor but, if stpclk# is asserted, the processor returns to the sleep state.
chapter 4 power management 13 23802e ? september 2000 amd duron ? processor data sheet preliminary information controller provides a bios-programmable register in which it can disconnect the processor from the amd system bus upon the occurrence of a stop grant special cycle. the system receives the special cycle request from the processor and, if there are no outstanding probes or data movements, the system deasserts connect to the processor. the processor detects the deassertion of connect on a rising edge of sysclk, and deasserts procrdy to the system. in return, the system asserts clkfwdrst in anticipation of reestablishing a connection at some later point. note: the system must disconnect the processor from the amd system bus before issuing the stop grant special cycle to the pci bus. the processor can receive an interrupt or stpclk# deassertion after it sends a stop grant special cycle to the system but before the disconnection actually occurs. in this case, the processor sends the connect special cycle to the system, rather than continuing with the disconnect sequence. the system cancels the disconnection. figure 4 shows the sequence of events from a system perspective, which leads to disconnecting the processor from the amd system bus and placing the processor in the stop grant state. figure 4. example system bus disconnection sequence the following sequence of events describes how the processor is placed in the stop grant state when bus disconnection is enabled within the system controller: 1. the peripheral controller asserts stpclk# to place the processor in the stop grant state. 2. when the processor receives stpclk#, it acknowledges the system by sending out a stop grant special bus cycle on the amd system bus. stop grant sbc stop grant sbc stpclk# connect procrdy clkfwdrst pci bus system bus
14 power management chapter 4 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 3. when the special cycle is received by the system controller, the system controller deasserts connect, initiating a bus disconnect to the processor. 4. the processor replies to the system controller by deasserting procrdy, approving the bus disconnect request. 5. the system controller asserts clkfwdrst to complete the bus disconnection sequence. 6. after the processor is disconnected from the bus, the system controller passes the stop grant special cycle along to the peripheral controller via the pci bus, notifying it that the processor is in the stop grant state. figure 5 shows the signal sequence of events that take the processor out of the stop grant state, reconnect the processor to the amd system bus, and put the processor into the full-on state. figure 5. exiting stop grant state/bus reconnection sequence the following sequence of events removes the processor from the stop grant state and reconnects it to the amd system bus: 1. the peripheral controller deasserts stpclk#, informing the processor of a wake event. 2. when the processor receives stpclk#, it asserts procrdy, notifying the system controller to reconnect to the bus. 3. the system controller asserts connect, telling the processor that it is connected to the amd system bus. 4. the system controller finally deasserts clkfwdrst, which synchronizes the forwarded clocks between the processor and the system controller. stpclk# procrdy connect clkfwdrst
chapter 4 power management 15 23802e ? september 2000 amd duron ? processor data sheet preliminary information connection state machines figure 6 and figure 7 describe the system and processor connection state machines, respectively. figure 6. system connection states condition 1 a disconnect is requested and probes are still pending 2 a disconnect is requested and no probes are pending 3 a connect special cycle from the processor 4 no probes are pending 5 procrdy is deasserted 6 a probe needs service 7 procrdy is asserted 8 3 sysclk periods after clkfwdrst is deasserted. although re c onnected to the system interface, the system must not issue any non -n op sysdc commands for a minimum of four sysclk periods after de a sserting clkfwdrst . action a deassert connect 8 sysclk periods after last probe/command sent bassert clkfwdrst c assert connect d deassert clkfwdrst disconnect pending connect disconnect requested reconnect pending probe pending 2 disconnect probe pending 1 1 3 2/a 4/a 5/b 3/c 7/d,c 8 6/c 7/d 8
16 power management chapter 4 amd duron ? processor data sheet 23802e ? september 2000 preliminary information figure 7. processor connection states condition 1 connect is deasserted by the system (for a previously sent halt or stop grant special cycle). 2 processor receives a wake-up event and must cancel the disconnect request. 3 deassert procrdy and slow down internal clocks. 4 processor wake-up event or connect asserted by system. 5 clkfwdrst is deasserted by the system 6 forward clocks start 3 sysclk periods after clkfwdrst is deasserted. action a clkfwdrst is asserted by the system. b issue a connect special cycle. c assert procrdy and return internal clocks to full speed connect disconnect pending disconnect connect pending 1 connect pending 2 1 3/a 4/c 5 6/b 2/b
chapter 5 thermal design 17 23802e ? september 2000 amd duron ? processor data sheet preliminary information 5 thermal design for information about thermal design, including layout and airflow considerations, see the amd thermal, mechanical, and chassis cooling design guide , order# 23794 and the cooling guidelines on www.amd.com. table 2 shows the thermal design power. the thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal vcc_core. thermal solutions must monitor the processor temperature to prevent the processor from exceeding its maximum die temperature. the maximum die temperature is specified through characterization at 90 c. table 2. thermal design power frequency (mhz) voltage maximum thermal power typical thermal power 600 1.6 v 26.07 w 23.40 w 650 27.87 w 25.02 w 700 29.66 w 26.63 w 750 31.46 w 28.25 w
18 thermal design chapter 5 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 6 electrical data 19 23802e ? september 2000 amd duron ? processor data sheet preliminary information 6 electrical data 6.1 conventions the conventions used in this chapter are as follows: current specified as being sourced by the processor is negative . current specified as being sunk by the processor is positive . 6.2 amd duron ? processor interface signal groupings the electrical data in this chapter is presented separately for each signal group. table 3 defines each group and the signals contained in each group. table 3. amd duron ? processor interface signal groupings signal group signals notes power vid[4:0], vcc_core, vcca, corefb, corefb# see ? voltage identification (vid[4:0]) ? on page 20, ? vid[4:0] pins ? on page 61, and ? vcca ac and dc characteristics ? on page 21. frequency fid[3:0] see ? frequency identification (fid[3:0]) ? on page 20 and ? fid[3:0] pins ? on page 58. system clocks sysclk, sysclk# (tied to clkin/clkin# and rstclk/rstclk#), pllbypassclk#, pllbypassclk see ? sysclk and sysclk# dc and ac characteristics ? on page 22. system bus saddin[14:2]#, saddout[14:2]#, saddinclk#, saddoutclk#, sfillval#, sdatainval#, sdataoutval#, sdata[63:0]#, sdatainclk[3:0]#, sdataoutclk[3:0]#, scheck[7:0]#, clkfwdrst, procrdy, connect see ? amd system bus ac and dc characteristics ? on page 25. southbridge reset#, intr, nmi, smi#, init#, a20m#, ferr, ignne#, stpclk#, flush# see ? general ac and dc characteristics ? on page 27. jtag tms, tck, trst#, tdi, tdo see ? general ac and dc characteristics ? on page 27. apic picd[1:0]#, picclk see ? apic pins ac and dc characteristics ? on page 28.
20 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 6.3 voltage identification (vid[4:0]) table 4 shows the vid[4:0] dc characteristics. for more information, see ? vid[4:0] pins ? on page 61. 6.4 frequency identification (fid[3:0]) table 5 shows the fid[3:0] dc characteristics. for more information, see ? fid[3:0] pins ? on page 58. test plltest#, pllmon1, pllmon2, scanclk1, scanclk2, scanshiften, scaninteval, analog these pins must be pulled down to vss. see ? general ac and dc characteristics ? on page 27. miscellaneous pllbypass#, dbreq#, dbrdy, pwrok see ? general ac and dc characteristics ? on page 27. table 3. amd duron ? processor interface signal groupings (continued) signal group signals notes table 4. vid[4:0] dc characteristics parameter description min max i ol output current low tbd v oh output high voltage 2.5 v* note: * the vid pins must not be pulled above this voltage by an external pullup resistor. table 5. fid[3:0] dc characteristics parameter description min max i ol output current low tbd v oh output high voltage 2.5 v* note: * the fid pins must not be pulled above this voltage by an external pullup resistor.
chapter 6 electrical data 21 23802e ? september 2000 amd duron ? processor data sheet preliminary information 6.5 vcca ac and dc characteristics table 6 shows the ac and dc characteristics for vcca. for more information, see ? vcca pin ? on page 61. 6.6 decoupling see the motherboard pga design guide , order# 90009, or contact your local amd office for information about the decoupling required on the motherboard for use with the amd duron ? processor. 6.7 operating ranges the amd duron processor is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in table 7. table 6. vcca ac and dc characteristics symbol parameter min max units v vcca vcca pin voltage (dc) 2.25 2.75 v i vcca vcca pin current 0 50 ma/ghz* v vcca-noise vcca pin voltage (ac) ? 100 +100 mv note: * measured at 2.5 v table 7. operating ranges parameter description min nominal max notes vcc_core processor core supply 600 ? 750 mhz 1.5 v 1.6 v 1.7 v 1 vcc_core sleep processor core supply in sleep state 1.2 v 1.3 v 1.4 v 2 t die temperature of processor die 90 o c notes: 1. for normal operating conditions (nominal vcc_core is 1.6 v) 2. for sleep state operating conditions for more information see the processor bios developer ? s guide , order# 21656.
22 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 6.8 absolute ratings the amd duron processor should not be subjected to conditions exceeding the absolute ratings listed in table 8, as such conditions may adversely affect long-term reliability or result in functional damage. 6.9 power dissipation table 9 shows the power and current of the processor during normal and reduced power states. 6.10 sysclk and sysclk# dc and ac characteristics table 10 shows the dc characteristics of the sysclk and sysclk# differential clocks. the sysclk signal represents clkin and rstclk tied together while the sysclk# signal represents clkin# and rstclk# tied together. figure 8 shows this condition. table 8. absolute ratings parameter description min max vcc_core amd duron processor core supply ? 0.5 v vcc_core max + 0.5 v vcca amd duron processor pll supply ? 0.5 v vcca max + 0.5 v v pin voltage on any signal pin ? 0.5 v vcc_core max + 0.5 v t storage storage temperature of processor ? 40 o c100 o c table 9. vcc_core voltage and current frequency (mhz) nominal voltage maximum voltage stop grant (maximum) 1 maximum i cc (power supply current) 2 die temperature 600 1.6 v 1.7 v 5 w 18.28 a 90 c 650 19.55 a 700 20.81 a 750 22.07 a notes: 1 measured at 1.3v for sleep state operating conditions 2. measured at nominal voltage
chapter 6 electrical data 23 23802e ? september 2000 amd duron ? processor data sheet preliminary information figure 8. sysclk and sysclk# differential clock signals table 11 shows the sysclk/sysclk# differential clock ac characteristics. figure 9 shows a sample waveform. table 10. sysclk and sysclk# dc characteristics symbol description min max units v threshold-dc crossing before transition is detected (dc) 400 mv v threshold-ac crossing before transition is detected (ac) 450 mv i leak_p leakage current through p-channel pullup to vcc_core ? 1ma i leak_n leakage current through n-channel pulldown to vss (ground) 1 ma v cross differential signal crossover vcc_core/2 +/ ? 100 mv c pin capacitance 4 12 pf v cross v threshold-dc = 400mv v threshold-ac = 450mv table 11. sysclk and sysclk# ac characteristics symbol description min max units notes clock frequency 50 100 mhz duty cycle 30% 70% ? t 1 period 10 ns 1, 2 t 2 high time 4 ns notes: 1. circuitry driving the sysclk and sysclk# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the pll to track the jitter. the ?20 db attenuation point, as measured into a 10-pf or 20-pf load must be less than 500 khz. 2. circuitry driving the sysclk and sysclk# inputs may purposely alter the sysclk and sysclk# period (spread spectrum clock generators). in no cases can the period violate the minimum specification above. sysclk and sysclk# inputs may vary from 100% of the specified period to 99% of the specified period at a maximum rate of 100 khz. 3. measured from 0.5 v to vcc_core 4. measured from vcc_core to 0.5 v
24 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information figure 9. sysclk waveform t 3 low time 4 ns t 4 fall time 500 ps 4 t 5 rise time 500 ps 3 period stability 300 ps table 11. sysclk and sysclk# ac characteristics (continued) symbol description min max units notes notes: 1. circuitry driving the sysclk and sysclk# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the pll to track the jitter. the ? 20 db attenuation point, as measured into a 10-pf or 20-pf load must be less than 500 khz. 2. circuitry driving the sysclk and sysclk# inputs may purposely alter the sysclk and sysclk# period (spread spectrum clock generators). in no cases can the period violate the minimum specification above. sysclk and sysclk# inputs may vary from 100% of the specified period to 99% of the specified period at a maximum rate of 100 khz. 3. measured from 0.5 v to vcc_core 4. measured from vcc_core to 0.5 v t 5 v threshold-ac v cross ? v threshold-ac t 2 t 3 t 4 t 1
chapter 6 electrical data 25 23802e ? september 2000 amd duron ? processor data sheet preliminary information 6.11 amd system bus ac and dc characteristics table 12 shows the dc characteristics of the amd system bus used by the amd duron processor. table 12. amd system bus dc characteristics symbol parameter condition min max units notes v ref dc input reference voltage (0.5*vcc_core) ? 50 (0.5*vcc_core) +50 mv 1 i vref_leak_p v ref tristate leakage pullup v in = v ref nominal ? 100 a i vref_leak_n v ref tristate leakage pulldown v in = v ref nominal +100 a v ih input high voltage v ref + 200 vcc_core + 500 mv v il input low voltage ? 500 v ref ? 200 mv v oh output high voltage i out = ? 200 a 0.85*vcc_core vcc_core+500 mv 2 v ol output low voltage i out = 1 ma ? 500 400 mv 2 i leak_p tristate leakage pullup v in = vss (ground) ? 1ma i leak_n tristate leakage pulldown v in = vcc_core nominal +1 ma c in input pin capacitance 4 12 pf 3 notes: 1. v ref : ? v ref is nominally set by a (1%) resistor divider from vcc_core. ? the suggested divider resistor values are 100 ohms over 100 ohms to produce a divisor of 0.50. ? example: vcc_core = 1.75v, v ref = 850mv (1.7 * 0.50). (processor pin sysvrefmode = low) ? peak-to-peak ac noise on v ref (ac) should not exceed 2% of v ref (dc). 2. specified at t = 90 c and vcc_core 3. the following processor inputs have twice the listed capacitance because they connect to two input pads ? sysclk, and sysclk#. sysclk connects to clkin/rstclk. sysclk# connects to clkin#/rstclk#. for more information, see table 18 on page 43 .
26 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 6.12 amd system bus ac characteristics the ac characteristics of the amd duron processor system bus are shown in table 13. the parameters are grouped based on the source or destination of the signals involved. table 13. amd system bus ac characteristics group symbol parameter min max units notes all signals t rise output rise slew rate 1 3 v/ns 1 t fall output fall slew rate 1 3 v/ns 1 forward clocks t skew- sameedge output skew with respect to the same clock edge 385 ps 2 t skew- diffedge output skew with respect to a different clock edge 770 ps 2 t su input data setup time 300 ps 3 t hd input data hold time 300 ps 3 c in capacitance on input clocks 4 12 pf c out capacitance on output clocks 4 12 pf sync 4 t val rstclk to output valid 250 2000 ps 5 t su setup to rstclk 500 ps 6 t hd hold from rstclk 1000 ps 6 notes: 1. rise and fall time ranges are guidelines over which the i/o has been characterized. 2. t skew-sameedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. t skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. input su and hd times are with respect to the appropriate clock forward group input clock. 4. the synchronous signals include procrdy, connect, clkfwdrst. 5. t val is rstclk rising edge to output valid for procrdy. test load ? 25pf. 6. t su is setup of connect/clkfwdrst to rising edge of rstclk. t hd is hold of connect/clkfwdrst from rising edge of rstclk.
chapter 6 electrical data 27 23802e ? september 2000 amd duron ? processor data sheet preliminary information 6.13 general ac and dc characteristics table 14 shows the ac and dc characteristics of the amd duron processor southbridge, jtag, test, and miscellaneous pins. table 14. general ac and dc characteristics* symbol parameter description condition min max units notes v ih input high voltage (vcc_core/2) + 200mv vcc_core + 300mv v1,2 v il input low voltage ? 300 350 mv 1,2 delta v rb hysteresis change in v ix 180 250 mv v oh output high voltage vcc_core ? 400 vcc_core + 300 mv v ol output low voltage ? 300 400 mv i leak_p tristate leakage pullup v in = vss (ground) ? 1ma i leak_n tristate leakage pulldown v in = vcc_core nominal 600 a i oh output high current ? 16 ma 4 i ol output low current 16 ma 4 t su sync input setup time 2.0 ns 5, 6 t hd sync input hold time 0.0 ps 5, 6 t delay output delay with respect to rstclk 0.0 6.1 ns 6 notes: * these parameters were not characterized at vcc_core sleep . 1. characterized across dc supply voltage range. 2. values specified at nominal vcc_core. scale parameters between vcc_core min and vcc_core max. 3. hysteresis values refer to the difference between initial and return switching points. 4. i ol and i oh are measured at v ol max and v oh min, respectively. 5. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 6. these are aggregate numbers. 7. edge rates indicate the range over which inputs were characterized. 8. in asynchronous operation, the signal must persist for this time to guarantee capture. 9. this value assumes rstclk frequency is 10ns ==> tbit = 2*frst. 10. the approximate value for standard case in normal mode operation. 11. this value is dependent on rstclk frequency, divisors, lowpower mode, and core frequency. 12. reassertions of the signal within this time are not guaranteed to be seen by the core. 13. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 14. this value assumes rstclk and k7clkout are running at the same frequency, though the processor is capable of other configurations.
28 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 6.14 apic pins ac and dc characteristics table 15 shows the ac and dc characteristics of the amd duron processor apic pins. t bit input time to acquire 20.0 ns 8,9 t rpt input time to reacquire 40.0 ns 10 ? 14 t rise signal rise time 1.0 3.0 v/ns 7 t fall signal fall time 1.0 3.0 v/ns 7 c pin pin capacitance 4 12 pf table 14. general ac and dc characteristics* (continued) symbol parameter description condition min max units notes notes: * these parameters were not characterized at vcc_core sleep . 1. characterized across dc supply voltage range. 2. values specified at nominal vcc_core. scale parameters between vcc_core min and vcc_core max. 3. hysteresis values refer to the difference between initial and return switching points. 4. i ol and i oh are measured at v ol max and v oh min, respectively. 5. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 6. these are aggregate numbers. 7. edge rates indicate the range over which inputs were characterized. 8. in asynchronous operation, the signal must persist for this time to guarantee capture. 9. this value assumes rstclk frequency is 10ns ==> tbit = 2*frst. 10. the approximate value for standard case in normal mode operation. 11. this value is dependent on rstclk frequency, divisors, lowpower mode, and core frequency. 12. reassertions of the signal within this time are not guaranteed to be seen by the core. 13. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 14. this value assumes rstclk and k7clkout are running at the same frequency, though the processor is capable of other configurations. table 15. apic pins ac and dc characteristics symbol parameter description condition min max units notes v ih input high voltage 1.7 2.625 v 1, 3 v il input low voltage ? 300 700 mv 1, 2 v oh output high voltage 2.625 v 3 notes: 1. characterized across dc supply voltage range 2. values specified at nominal vdd (1.5 v). scale parameters with vdd 3. 2.625 v = 2.5 v + 5% maximum 4. edge rates indicate the range over which inputs were characterized
chapter 6 electrical data 29 23802e ? september 2000 amd duron ? processor data sheet preliminary information v ol output low voltage ? 300 400 mv i leak_p tristate leakage pullup v in = vss (ground) ? 1ma i leak_n tristate leakage pulldown v in = 2.5 v 1ma i ol output low current v ol max 6ma t rise signal rise time 1.0 3.0 v/ns 4 t fall signal fall time 1.0 3.0 v/ns 4 c pin pin capacitance 4 12 pf table 15. apic pins ac and dc characteristics symbol parameter description condition min max units notes notes: 1. characterized across dc supply voltage range 2. values specified at nominal vdd (1.5 v). scale parameters with vdd 3. 2.625 v = 2.5 v + 5% maximum 4. edge rates indicate the range over which inputs were characterized
30 electrical data chapter 6 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 7 signal and power-up requirements 31 23802e ? september 2000 amd duron ? processor data sheet preliminary information 7 signal and power-up requirements this chapter describes the amd duron ? processor power-up requirements during system turn-on and warm resets. these requirements can be adhered to with minor motherboard modifications or the usage of a recommended system power supply (silver box) for the specific motherboard. this information is applicable to all current socket a motherboards. 7.1 power-up requirements signal sequence and timing description the amd duron processor requires that the system clocks (sysclk/sysclk#) to the processor be running prior to the assertion of pwrok. pwrok is an output of the voltage regulation circuit on the motherboard indicating that vcc_core is valid to the processor. figure 10 on page 32 shows the relationship between key signals in the system during a power-up sequence. this figure details the requirements of the processor. note: figure 10 represents several signals generically by using names not necessarily consistent with any pin lists or schematics.
32 signal and power-up requirements chapter 7 amd duron ? processor data sheet 23802e ? september 2000 preliminary information figure 10. signal relationship requirements during power-up sequence required sequence. many southbridges (peripheral controllers) assert reset# and nb_reset# (for example, pcirst#) as soon as possible after receiving power. the system clock generator produces a clock soon after it has valid power (see the specific system clock data sheets for more information). typically, they generate the system clocks 3ms after receiving a valid power level (that is, 3.3v) from the motherboard. in addition, the motherboard must pull the open-drain system clocks (sysclk/sysclk#) to vcc_core. because the amd atx power supply specification requires 3.3v to be valid prior to vcc_core, the motherboard must assert pwrok only after a valid system clock is generated. to accommodate a variety of system parameters, it is recommended that pwrok should assert only after at least 3ms past a valid vcc_core (a valid system clock). when pwrok is asserted, the processor pll turns on and begins to lock. after a specified period to ensure the pll has locked, the reset signals can be deasserted. 3.3v supply vcca (2.5v) (for pll) reset# 1.6v supply (processor core) nb_reset# pwrok system clock 2 1 3 4 5 6
chapter 7 signal and power-up requirements 33 23802e ? september 2000 amd duron ? processor data sheet preliminary information timing requirements. the signal timing requirements are as follows: 1. reset# must be asserted before pwrok is asserted the amd duron processor does not set the correct clock multiplier if pwrok is asserted prior to a reset# assertion. it is recommended that reset# be asserted at least 10ns prior to the assertion of pwrok. 2. all motherboard power supplies should be ramped before the assertion of pwrok. the processor core voltage, vcc_core, should have a stable voltage (for example, 1.7v) as indicated by the voltage id (vid) prior to pwrok assertion. before pwrok assertion, the amd duron processor is clocked by a ring oscillator. this minimum time is not specified. the amd duron processor pll is powered by vcca. the processor pll does not lock if vcca is not high enough for the processor logic to switch for some period before pwrok is asserted. the recommended minimum time before pwrok assertion is 5 s . 3. the system clock (sysclk/sysclk#) should be running before pwrok is asserted. when pwrok is asserted, the amd duron processor switches from driving the internal processor clock grid from the ring oscillator to driving from the pll. the reference system clock should be valid at this time. if it is not valid, the subsequent requirements may be undermined. it is recommended that pwrok be asserted 3ms after the system clocks are running. 4. pwrok assertion to deassertion of reset# the duration of reset during cold boots is intended to satisfy the time it takes for the pll to lock with a less than 1-ns phase error. the amd duron processor pll begins to run after pwrok is asserted and the internal clock grid is switched from the ring oscillator to the pll. the pll lock time may take from hundreds of nanoseconds to tens of microseconds. it is recommended that the minimum time between pwrok assertion to the deassertion of reset# be at least 1.5ms. 5. pwrok should be monotonic. the processor should not switch between the ring oscillator and the pll after the initial assertion of pwrok.
34 signal and power-up requirements chapter 7 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 6. nb_reset# should be asserted (causing connect to also assert) before reset# is deasserted. if nb_reset# does not assert until after reset# has deasserted, the processor misinterprets the connect assertion (due to nb_reset# being asserted) as the beginning of the sip transfer (see ? serial initialization packet (sip) protocol ? on page 34). there must be sufficient overlap in the resets to ensure that connect has a chance to be sampled asserted by the processor in advance of the processor coming out of reset. clock multiplier selection (fid[3:0]) when reset# is deasserted, the processor selects the processor clock ratio (multiplier) by driving the fid[3:0] signals. the system samples the clock multiplier value from fid[3:0]. for more information, see ? fid[3:0] pins ? on page 58. the system samples the processor clock multiplier value and other system configuration information when reset# deasserts, and uses this value to correctly initialize and configure the system bus. the system sends the processor its initialization state in a serial packet using the serial initialization packet (sip) protocol. this protocol uses the procrdy, connect, and clkfwdrst signals, which are synchronous to sysclk. serial initialization packet (sip) protocol. figure 11 on page 35 shows the protocol for a typical sip transfer to the processor after reset. table 16 on page 35 describes the requirements for the sip transfer from the system to the processor. processors and northbridges are designed to adhere to the following protocol and do not require motherboard intervention.
chapter 7 signal and power-up requirements 35 23802e ? september 2000 amd duron ? processor data sheet preliminary information figure 11. typical sip protocol sequence table 16. sip protocol states and actions state action 1 when nb_reset# and reset# are asserted, the system asserts connect and clkfwdrst and the processor asserts procrdy. 2 when nb_reset# is deasserted, the system deasserts connect, but continues to assert clkfwdrst. when reset# is deasserted, the processor deasserts procrdy and is ready for initialization (via the sip protocol). note: the system must be out of reset before the processor deasserts procrdy 3 after one or more sysclk periods after the deassertion of procrdy, the system deasserts clkfwdrst. (states 3 & 4 are performed for amd system bus legacy reasons) 4 after one or more sysclk periods after the deassertion of clkfwdrst, the system again asserts clkfwdrst 5 either at the assertion of clkfwdrst or one or more sysclk periods later, the processor expects the start bit (connect asserted) of the sip. the system delivers the sip containing the processor clock-forwarding initialization state over connect as seen in figure 11 on page 35. after the sip is transferred, the system asserts and holds connect. this indicates the end of the sip transfer to the processor. 6 one or more sysclk periods after receiving the sip, the processor asserts procrdy to indicate to the system that it has received the sip, initialized itself, and is ready. 7 one or more sysclk periods after the assertion of procrdy, the system deasserts clkfwdrst. 8 two sysclk periods after clkfwdrst is sampled deasserted, the processor drives its forward clocks. star t sip 1 sip n cm d 0ns 25ns 50ns 75ns 100ns 125ns nb_reset# reset# clkfwdrst connect procrdy sysclk saddoutclk# s addout[14:2]#
36 signal and power-up requirements chapter 7 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 7.2 processor warm reset requirements the amd duron ? processor and northbridge reset pins warm resets differ from cold resets because the motherboard power supplies are already stable and the processor pll is locked. requirements differ for warm resets because the amd duron processor may be in a system sleep state when reset# asserts. duration of reset# as a function of low power ratio. although the processor pll is already locked, the processor requires that reset# be asserted for some period to ensure that procrdy can assert without glitching. the amd duron processor clock grid is slowed down to a ratio of as little as 1/128th of its normal frequency. therefore, it takes a corresponding length of time to assert procrdy. in addition, in order to avoid glitching procrdy, it is necessary to assert reset# for a duration that the amd duron processor can synchronize reset# into the processor clock domain. table 17 shows the minimum reset# duration to ensure the proper procrdy pin behavior as a function of the low power ratio. assertion of reset# to deassertion of nb_reset#. when the northbridge exits reset, the processor must have procrdy asserted in response to the reset# assertion or else the northbridge may start the sip transfer (because some northbridges sample only for a low procrdy level). this scenario implies a dependency from reset#=0 to nb_reset#=1: table 17. reset# minimum duration processor version low power divisor (recommended) reset# min assertion time amd duron ? processor 128 2.5 s @100mhz sysclk
chapter 8 mechanical data 37 23802e ? september 2000 amd duron ? processor data sheet preliminary information 8 mechanical data 8.1 introduction the amd duron ? processor connects to the motherboard through a pga socket named socket a. for more information, see the amd athlon processor socket 462 application note , order# 90020. 8.2 pinout diagram the pin location designations for the socket a connector are shown in figure 12 on page 38. voided (plugged) pin locations should have a base that accepts a contact, but the top plate of socket a should not have pin openings. the exceptions are the two plugs on the outside corners, which should be permanently closed and not accommodate a contact. it is permissible, if necessary for manufacturing reasons, to place a contact in the base at plug sites ( except for the two plugs on the outside corners). socket a has 462 pin sites, with 11 plugs total. for more information, see chapter 9, ? pin descriptions ? on page 41. in addition, figure 12 shows the socket a package side view and top view.
38 mechanical data chapter 8 amd duron ? processor data sheet 23802e ? september 2000 preliminary information figure 12. pga package, top, side, and bottom views
chapter 8 mechanical data 39 23802e ? september 2000 amd duron ? processor data sheet preliminary information 8.3 socket tabs for heatsink clips figure 13 shows the socket tab required on socket a. these features are required to support a 300g heatsink. figure 14 on page 40 shows the socket tab side view. figure 13. socket a with outline of socket and heatsink tab note: measurements are in mm
40 mechanical data chapter 8 amd duron ? processor data sheet 23802e ? september 2000 preliminary information figure 14. socket a heatsink tab side view
chapter 9 pin descriptions 41 23802e ? september 2000 amd duron ? processor data sheet preliminary information 9 pin descriptions 9.1 introduction figure 15 on page 42 shows the staggered pin grid array (spga) for the amd duron ? processor. because some of the pin names are too long to fit in the grid, they are abbreviated. table 18 on page 43 lists all the pins in alphabetical order by pin name, along with the abbreviation where necessary.
42 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728 293031323334353637 a sao# 12 sao#5 sao#3 sd#55 sd#61 sd#53 sd#63 sd#62 sck#7 sd#57 sd#39 sd#35 sd#34 sd#44 sck#5 sdoc# 2 sd#40 sd#30 a b vss101 vcc 100 vss100 vcc99 vss99 vcc98 vss98 vcc97 vss97 vcc96 vss96 vcc95 vss95 vcc94 vss94 vcc92 vss92 vcc91 b c sao#7sao#9sao#8sao#2sd#54sdoc# 3 sck#6 sd#51 sd#60 sd#59 sd#56 sd#37 sd#47 sd#38 sd#45 sd#43 sd#42 sd#41 sdoc# 1 c d vcc90 vcc89 vss91 vcc88 vss90 vcc87 vss89 vcc86 vss88 vcc85 vss87 vcc84 vss86 vcc82 vss85 vcc81 vss84 vss83 d e sao#11 sao- clk# sao#4 sao#6 sd#52 sd#50 sd#49 sdic#3 sd#48 sd#58 sd#36 sd#46 sck#4 sdic#2 sd#33 sd#32 sck#3 sd#31 sd#22 e f vss81 vss80 vss79 nc59 vss78 vcc80 vss77 vcc79 vss76 vcc78 vss75 vcc77 vss74 vcc76 nc58 vcc75 vcc74 vcc73 f g sao# 10 sao# 14 sao# 13 key8 nc19 nc20 key6 nc nc key4 nc21 nc22 nc23 sd#20 sd#23 sd#21 g h vcc71 vcc70 nc64 nc65 nc60 vcc1 vss1 vcc2 vss2 vcc3 vss3 vcc4 vss4 nc61 nc62 nc63 vss73 vss72 h j sao#0 sao#1 nc25 vid(4) nc24 sd#19 sdic#1 sd#29 j k vss70 vss69 vss68 nc67 nc66 vcc69 vcc68 vcc67 k l vid(0) vid(1) vid(2) vid(3) nc27 sd#26 sck#2 sd#28 l m vcc66 vcc64 vcc65 vcc5 vss5 vss67 vss66 vss65 m n picclk picd#0 picd#1 key10 nc28 sd#25 sd#27 sd#18 n p vss64 vss63 vss62 vss6 vcc6 vcc63 vcc62 vcc61 p q tck tms scnsn nc29 sd#24 sd#17 sd#16 q r vcc59 vcc58 vcc57 vcc7 vss7 vss61 vss59 vss58 r s scnck1 scninv scnck2 nc31 nc30 sd#7 sd#15 sd#6 s t vss57 vss56 vss55 vss8 vcc8 vcc56 vcc55 vcc54 t u tdi trst# tdo nc33 nc32 sd#5 sd#4 sck#0 u v vcc53 vcc52 vcc51 vcc9 vss9 vss54 vss53 vss52 v w fid(0) fid(1) vref_s nc35 nc34 sdic#0 sd#2 sd#1 w x vss51 vss50 vss48 vss10 vcc10 vcc50 vcc48 vcc47 x y fid(2) fid(3) nc37 key12 nc36 sck#1 sd#3 sd#12 y z vcc46 vcc45 vcc44 vcc11 vss11 vss47 vss46 vss45 z aa dbrdy dbreq # svrfm nc1 sd#8 sd#0 sd#13 aa ab vss44 vss43 vss42 vss12 vcc12 vcc43 vcc42 vcc41 ab ac stpc# pltst# zn vcc_z nc2 sd#10 sd#14 sd#11 ac ad vcc40 vcc39 vcc37 nc42 nc41 vss41 vss40 vss39 ad ae a20m# pwrok zp vss_z nc3 sai#5 sdoc# 0 sd#9 ae af vss38 vss37 nc47 nc48 nc43 vss13 vcc13 vss14 vcc14 vss15 vcc15 vss16 vcc16 nc44 nc45 nc46 vcc36 vcc35 af ag ferr# reset# nc9 key14 corefb corefb # key16 nc nc nc6 nc7 key18 nc8 sai#2 sai#11 sai#7 ag ah vcc34 vcc33 nc50 vcc32 vss35 vcc31 vss34 vcc30 vss33 vcc29 vss32 vcc27 vss31 nc49 vss30 vss29 vss27 ah aj ignne# init# vcc101 nc51 nc52 nc10 anlog nc11 nc12 nc13 clkfr vcca plbyp# nc15 nc sfillv# saic# sai#6 sai#3 aj ak vss26 vss25 vss103 nc53 vcc25 vss23 vcc24 vss22 vcc23 vss21 vcc22 vss20 vcc21 vss19 vcc20 vss18 vcc19 vcc18 ak al intr flush# vcc26 nc54 nc55 nc16 plmn2 plbyc# clkin# rclk# k7co cnnct nc nc sai#1 sdov# sai#8 sai#4 sai#10 al am vcc93 vss102 vss104 nc56 vcc83 vss93 vcc72 vss82 vcc60 vss71 vcc49 vss60 vcc38 vss49 vcc28 vss28 vcc17 vss17 am an nmi smi# nc57 nc18 nc17 plmn1 plbyc clkin rclk k7co# prcrdy nc nc sai#12 sai#14 sdinv# sai#13 sai#9 an 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 amd duron ? processor topside view figure 15. amd duron ? processor pin diagram ? topside view
chapter 9 pin descriptions 43 23802e ? september 2000 amd duron ? processor data sheet preliminary information table 18. pin name abbreviations abbreviation full name pin abbreviation full name pin a20m# ae1 nc3 ae31 anlog analog aj13 nc6 ag23 clkfr clkfwdreset aj21 nc7 ag25 clkin an17 nc8 ag31 clkin# al17 nc9 ag5 cnnct connect al23 nc10 a j11 corefb ag11 nc11 a j15 corefb# ag13 nc12 aj17 dbrdy aa1 nc13 a j19 dbreq# aa3 nc15 aj27 nc ag19 nc16 al11 nc g21 nc17 an11 ferr ag1 nc18 an9 fid[0] w1 nc19 g11 fid[1] w3 nc20 g13 fid[2] y1 nc21 g27 fid[3] y3 nc22 g29 flush# al3 nc23 g31 nc ag21 nc24 j31 nc g19 nc25 j5 ignne# aj1 nc27 l31 init# aj3 nc28 n31 intr al1 nc29 q31 k7co k7clkout al21 nc30 s31 k7co# k7clkout# an21 nc31 s7 key4 g25 nc32 u31 key6 g17 nc33 u7 key8 g9 nc34 w31 key10 n7 nc35 w7 key12 y7 nc36 y31 key14 ag7 nc37 y5 key16 ag15 nc41 ad30 key18 ag29 nc42 ad8 nc al25 nc43 af10 nc al27 nc44 af28 nc an25 nc45 af30 nc an27 nc46 af32 nc1 aa31 nc47 af6 nc2 ac31 nc48 af8
44 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information nc49 ah30 stpc# stpclk# ac1 nc50 ah8 nc aj29 nc51 aj7 sai#1 saddin[1]# al29 nc52 aj9 sai#2 saddin[2]# ag33 nc53 ak8 sai#3 saddin[3]# aj37 nc54 al7 sai#4 saddin[4]# al35 nc55 al9 sai#5 saddin[5]# ae33 nc56 am8 sai#6 saddin[6]# aj35 nc57 an7 sai#7 saddin[7]# ag37 nc58 f30 sai#8 saddin[8]# al33 nc59 f8 sai#9 saddin[9]# an37 nc60 h10 sai#10 saddin[10]# al37 nc61 h28 sai#11 saddin[11]# ag35 nc62 h30 sai#12 saddin[12]# an29 nc63 h32 sai#13 saddin[13]# an35 nc64 h6 sai#14 saddin[14]# an31 nc65 h8 saic# saddinclk# aj33 nc66 k30 sao#0 saddout[0]# j1 nc67 k8 sao#1 saddout[1]# j3 nmi an3 sao#2 saddout[2]# c7 picclk n1 sao#3 saddout[3]# a7 picd#0 picd[0]# n3 sao#4 saddout[4]# e5 picd#1 picd[1]# n5 sao#5 saddout[5]# a5 plbyp# pllbypass# aj25 sao#6 saddout[6]# e7 plbyc pllbypassclk an15 sao#7 saddout[7]# c1 plbyc# pllbypassclk# al15 sao#8 saddout[8]# c5 plmn1 pllmon1 an13 sao#9 saddout[9]# c3 plmn2 pllmon2 al13 sao#10 saddout[10]# g1 pltst# plltest# ac3 sao#11 saddout[11]# e1 prcrdy procready an23 sao#12 saddout[12]# a3 pwrok ae3 sao#13 saddout[13]# g5 reset# ag3 sao#14 saddout[14]# g3 rclk rstclk an19 saoclk# saddoutclk# e3 rclk# rstclk# al19 sck#0 scheck[0]# u37 scnck1 scanclk1 s1 sck#1 scheck[1]# y33 scnck2 scanclk2 s5 sck#2 scheck[2]# l35 scninv scaninteval s3 sck#3 scheck[3]# e33 scnsn scanshiften q5 sck#4 scheck[4]# e25 smi# an5 sck#5 scheck[5]# a31 table 18. pin name abbreviations (continued) abbreviation full name pin abbreviation full name pin
chapter 9 pin descriptions 45 23802e ? september 2000 amd duron ? processor data sheet preliminary information sck#6 scheck[6]# c13 sd#37 sdata[37]# c23 sck#7 scheck[7]# a19 sd#38 sdata[38]# c27 sd#0 sdata[0]# aa35 sd#39 sdata[39]# a23 sd#1 sdata[1]# w37 sd#40 sdata[40]# a35 sd#2 sdata[2]# w35 sd#41 sdata[41]# c35 sd#3 sdata[3]# y35 sd#42 sdata[42]# c33 sd#4 sdata[4]# u35 sd#43 sdata[43]# c31 sd#5 sdata[5]# u33 sd#44 sdata[44]# a29 sd#6 sdata[6]# s37 sd#45 sdata[45]# c29 sd#7 sdata[7]# s33 sd#46 sdata[46]# e23 sd#8 sdata[8]# aa33 sd#47 sdata[47]# c25 sd#9 sdata[9]# ae37 sd#48 sdata[48]# e17 sd#10 sdata[10]# ac33 sd#49 sdata[49]# e13 sd#11 sdata[11]# ac37 sd#50 sdata[50]# e11 sd#12 sdata[12]# y37 sd#51 sdata[51]# c15 sd#13 sdata[13]# aa37 sd#52 sdata[52]# e9 sd#14 sdata[14]# ac35 sd#53 sdata[53]# a13 sd#15 sdata[15]# s35 sd#54 sdata[54]# c9 sd#16 sdata[16]# q37 sd#55 sdata[55]# a9 sd#17 sdata[17]# q35 sd#56 sdata[56]# c21 sd#18 sdata[18]# n37 sd#57 sdata[57]# a21 sd#19 sdata[19]# j33 sd#58 sdata[58]# e19 sd#20 sdata[20]# g33 sd#59 sdata[59]# c19 sd#21 sdata[21]# g37 sd#60 sdata[60]# c17 sd#22 sdata[22]# e37 sd#61 sdata[61]# a11 sd#23 sdata[23]# g35 sd#62 sdata[62]# a17 sd#24 sdata[24]# q33 sd#63 sdata[63]# a15 sd#25 sdata[25]# n33 sdic#0 sdatainclk[0]# w33 sd#26 sdata[26]# l33 sdic#1 sdatainclk[1]# j35 sd#27 sdata[27]# n35 sdic#2 sdatainclk[2]# e27 sd#28 sdata[28]# l37 sdic#3 sdatainclk[3]# e15 sd#29 sdata[29]# j37 sdinv# sdatainvalid# an33 sd#30 sdata[30]# a37 sdoc#0 sdataoutclk[0]# ae35 sd#31 sdata[31]# e35 sdoc#1 sdataoutclk[1]# c37 sd#32 sdata[32]# e31 sdoc#2 sdataoutclk[2]# a33 sd#33 sdata[33]# e29 sdoc#3 sdataoutclk[3]# c11 sd#34 sdata[34]# a27 sdov# sdataoutvalid# al31 sd#35 sdata[35]# a25 sfillv# sfillval# aj31 sd#36 sdata[36]# e21 svrfm sysvrefmode aa5 table 18. pin name abbreviations (continued) abbreviation full name pin abbreviation full name pin
46 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information tck q1 vcc35 vcc_core35 af36 tdi u1 vcc36 vcc_core36 af34 tdo u5 vcc37 vcc_core37 ad6 tms q3 vcc38 vcc_core38 am26 trst# u3 vcc39 vcc_core39 ad4 vcc1 vcc_core1 h12 vcc40 vcc_core40 ad2 vcc2 vcc_core2 h16 vcc41 vcc_core41 ab36 vcc3 vcc_core3 h20 vcc42 vcc_core42 ab34 vcc4 vcc_core4 h24 vcc43 vcc_core43 ab32 vcc5 vcc_core5 m8 vcc44 vcc_core44 z6 vcc6 vcc_core6 p30 vcc45 vcc_core45 z4 vcc7 vcc_core7 r8 vcc46 vcc_core46 z2 vcc8 vcc_core8 t30 vcc47 vcc_core47 x36 vcc9 vcc_core9 v8 vcc48 vcc_core48 x34 vcc10 vcc_core10 x30 vcc49 vcc_core49 am22 vcc11 vcc_core11 z8 vcc50 vcc_core50 x32 vcc12 vcc_core12 ab30 vcc51 vcc_core51 v6 vcc13 vcc_core13 af14 vcc52 vcc_core52 v4 vcc14 vcc_core14 af18 vcc53 vcc_core53 v2 vcc15 vcc_core15 af22 vcc54 vcc_core54 t36 vcc16 vcc_core16 af26 vcc55 vcc_core55 t34 vcc17 vcc_core17 am34 vcc56 vcc_core56 t32 vcc18 vcc_core18 ak36 vcc57 vcc_core57 r6 vcc19 vcc_core19 ak34 vcc58 vcc_core58 r4 vcc20 vcc_core20 ak30 vcc59 vcc_core59 r2 vcc21 vcc_core21 ak26 vcc60 vcc_core60 am18 vcc22 vcc_core22 ak22 vcc61 vcc_core61 p36 vcc23 vcc_core23 ak18 vcc62 vcc_core62 p34 vcc24 vcc_core24 ak14 vcc63 vcc_core63 p32 vcc25 vcc_core25 ak10 vcc64 vcc_core64 m4 vcc26 vcc_core26 al5 vcc65 vcc_core65 m6 vcc27 vcc_core27 ah26 vcc66 vcc_core66 m2 vcc28 vcc_core28 am30 vcc67 vcc_core67 k36 vcc29 vcc_core29 ah22 vcc68 vcc_core68 k34 vcc30 vcc_core30 ah18 vcc69 vcc_core69 k32 vcc31 vcc_core31 ah14 vcc70 vcc_core70 h4 vcc32 vcc_core32 ah10 vcc71 vcc_core71 h2 vcc33 vcc_core33 ah4 vcc72 vcc_core72 am14 vcc34 vcc_core34 ah2 vcc73 vcc_core73 f36 table 18. pin name abbreviations (continued) abbreviation full name pin abbreviation full name pin
chapter 9 pin descriptions 47 23802e ? september 2000 amd duron ? processor data sheet preliminary information vcc74 vcc_core74 f34 vss100 b6 vcc75 vcc_core75 f32 vss101 b2 vcc76 vcc_core76 f28 vss102 am4 vcc77 vcc_core77 f24 vss103 ak6 vcc78 vcc_core78 f20 vss104 am6 vcc79 vcc_core79 f16 vss11 z30 vcc80 vcc_core80 f12 vss12 ab8 vcc81 vcc_core81 d32 vss13 af12 vcc82 vcc_core82 d28 vss14 af16 vcc83 vcc_core83 am10 vss15 af20 vcc84 vcc_core84 d24 vss16 af24 vcc85 vcc_core85 d20 vss17 am36 vcc86 vcc_core86 d16 vss18 ak32 vcc87 vcc_core87 d12 vss19 ak28 vcc88 vcc_core88 d8 vss2 h18 vcc89 vcc_core89 d4 vss20 ak24 vcc90 vcc_core90 d2 vss21 ak20 vcc91 vcc_core91 b36 vss22 ak16 vcc92 vcc_core92 b32 vss23 ak12 vcc93 vcc_core93 am2 vss25 ak4 vcc94 vcc_core94 b28 vss26 ak2 vcc95 vcc_core95 b24 vss27 ah36 vcc96 vcc_core96 b20 vss28 am32 vcc97 vcc_core97 b16 vss29 ah34 vcc98 vcc_core98 b12 vss3 h22 vcc99 vcc_core99 b8 vss30 ah32 vcc100 vcc_core100 b4 vss31 ah28 vcc101 vcc_core101 aj5 vss32 ah24 vcc_z ac7 vss33 ah20 vcca aj23 vss34 ah16 vid[0] l1 vss35 ah12 vid[1] l3 vss37 af4 vid[2] l5 vss38 af2 vid[3] l7 vss39 ad36 vid[4] j7 vss4 h26 vref_s vref_sys w5 vss40 ad34 vss_z ae7 vss41 ad32 vss1 h14 vss42 ab6 vss10 x8 vss43 ab4 table 18. pin name abbreviations (continued) abbreviation full name pin abbreviation full name pin
48 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information vss44 ab2 vss8 t8 vss45 z36 vss80 f4 vss46 z34 vss81 f2 vss47 z32 vss82 am16 vss48 x6 vss83 d36 vss49 am28 vss84 d34 vss5 m30 vss85 d30 vss50 x4 vss86 d26 vss51 x2 vss87 d22 vss52 v36 vss88 d18 vss53 v34 vss89 d14 vss54 v32 vss9 v30 vss55 t6 vss90 d10 vss56 t4 vss91 d6 vss57 t2 vss92 b34 vss58 r36 vss93 am12 vss59 r34 vss94 b30 vss6 p8 vss95 b26 vss60 am24 vss96 b22 vss61 r32 vss97 b18 vss62 p6 vss98 b14 vss63 p4 vss99 b10 vss64 p2 zn ac5 vss65 m36 zp ae5 vss66 m34 vss67 m32 vss68 k6 vss69 k4 vss7 r30 vss70 k2 vss71 am20 vss72 h36 vss73 h34 vss74 f26 vss75 f22 vss76 f18 vss77 f14 vss78 f10 vss79 f6 table 18. pin name abbreviations (continued) abbreviation full name pin abbreviation full name pin
chapter 9 pin descriptions 49 23802e ? september 2000 amd duron ? processor data sheet preliminary information 9.2 pin list table 19 cross-references the socket a pin location to the signal name. the ? l ? (level) column shows the electrical specification for this pin. ? p ? indicates a push-pull mode driven by a single source. ? o ? indicates open-drain mode that allows devices to share the pin. note: the socket a amd duron processor supports push-pull drivers. for more information, see ?push-pull (pp) drivers? on page 6. the ? p ? (port) column indicates if this signal is an input (i), output (o), or bidirectional (b) signal. the ? r ? (reference) column indicates if this clock-forwarded signal should be referenced to the vss (g) or vcc_core (p) planes for the purpose of providing proper current return paths for the signal routes. for more information, see the motherboard pga design guide , order# 90009. the description column contains a cross-reference to a page with more information in the ? detailed pin descriptions ? (which starts on page 57). table 19. socket a pin cross-reference by pin location pin name description l p r pin name description l p r a1 no pin page 60 - - - b2 vss - - - a3 saddout[12]# p o g b4 vcc_core - - - a5 saddout[5]# p o g b6 vss - - - a7 saddout[3]# p o g b8 vcc_core - - - a9sdata[55]# pbpb10vss --- a11sdata[61]# pbpb12vcc_core --- a13sdata[53]# pbgb14vss --- a15 sdata[63]# p b g b16 vcc_core - - - a17 sdata[62]# p b g b18 vss - - - a19 scheck[7]# page 61 p b g b20 vcc_core - - - a21sdata[57]# pbgb22vss --- a23sdata[39]# pbgb24vcc_core ---
50 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information a25sdata[35]# pbpb26vss --- a27sdata[34]# pbpb28vcc_core --- a29 sdata[44]# p b g b30 vss - - - a31 scheck[5]# page 61 p b g b32 vcc_core - - - a33sdataoutclk[2]# pop b34vss - - - a35 sdata[40]# p b g b36 vcc_core - - - a37 sdata[30]# p b p c1 saddout[7]# p o g d2 vcc_core - - - c3 saddout[9]# p o g d4 vcc_core - - - c5 saddout[8]# p o g d6 vss - - - c7 saddout[2]# p o g d8 vcc_core - - - c9sdata[54]# pbpd10vss --- c11sdataoutclk[3]# pogd12vcc_core --- c13 scheck[6]# page 61 p b g d14 vss - - - c15sdata[51]# pbpd16vcc_core --- c17 sdata[60]# p b g d18 vss - - - c19sdata[59]# pbgd20vcc_core --- c21sdata[56]# pbgd22vss --- c23sdata[37]# pbpd24vcc_core --- c25sdata[47]# pbgd26vss --- c27sdata[38]# pbgd28vcc_core --- c29 sdata[45]# p b g d30 vss - - - c31 sdata[43]# p b g d32 vcc_core - - - c33 sdata[42]# p b g d34 vss - - - c35sdata[41]# pbgd36vss --- c37 sdataoutclk[1]# p o g e1 saddout[11]# p o p f2 vss - - - e3 saddoutclk# p o g f4 vss - - - e5 saddout[4]# p o p f6 vss - - - e7 saddout[6]# p o g f8 nc pin page 60 - - - e9sdata[52]# pbpf10vss --- e11sdata[50]# pbpf12vcc_core --- e13 sdata[49]# p b g f14 vss - - - e15 sdatainclk[3]# p i g f16 vcc_core - - - table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
chapter 9 pin descriptions 51 23802e ? september 2000 amd duron ? processor data sheet preliminary information e17sdata[48]# pbp f18vss - - - e19sdata[58]# pbgf20vcc_core --- e21sdata[36]# pbpf22vss --- e23 sdata[46]# p b p f24 vcc_core - - - e25 scheck[4]# page 61 p b p f26 vss - - - e27 sdatainclk[2]# p i g f28 vcc_core - - - e29 sdata[33]# p b p f30 nc pin page 60 - - - e31sdata[32]# pbpf32vcc_core --- e33 scheck[3]# page 61 p b p f34 vcc_core - - - e35sdata[31]# pbpf36vcc_core --- e37 sdata[22]# p b g g1 saddout[10]# p o p h2 vcc_core - - - g3 saddout[14]# p o g h4 vcc_core - - - g5 saddout[13]# p o g h6 nc pin page 60 - - - g7 key pin page 59 - - - h8 nc pin page 60 - - - g9 key pin page 59 - - - h10 nc pin page 60 - - - g11 nc pin page 60 - - - h12 vcc_core - - - g13 nc pin page 60 - - - h14 vss - - - g15 key pin page 59 - - - h16 vcc_core - - - g17 key pin page 59 - - - h18 vss - - - g19 nc pin page 60 - - - h20 vcc_core - - - g21 nc pin page 60 - - - h22 vss - - - g23 key pin page 59 - - - h24 vcc_core - - - g25 key pin page 59 - - - h26 vss - - - g27 nc pin page 60 - - - h28 nc pin page 60 - - - g29 nc pin page 60 - - - h30 nc pin page 60 - - - g31 nc pin page 60 - - - h32 nc pin page 60 - - - g33sdata[20]# pbgh34vss --- g35sdata[23]# pbgh36vss --- g37 sdata[21]# p b g j1 saddout[0]# page 60 p o - k2 vss - - - j3 saddout[1]# page 60 p o - k4 vss - - - j5 nc pin page 60 - - - k6 vss - - - j7 vid[4] page 61 o o - k8 nc pin page 60 - - - table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
52 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information j31 nc pin page 60 - - - k30 nc pin page 60 - - - j33sdata[19]# pbgk32vcc_core --- j35 sdatainclk[1]# p i p k34 vcc_core - - - j37sdata[29]# pbpk36vcc_core --- l1 vid[0] page 61 o o - m2 vcc_core - - - l3 vid[1] page 61 o o - m4 vcc_core - - - l5 vid[2] page 61 o o - m6 vcc_core - - - l7 vid[3] page 61 o o - m8 vcc_core - - - l31 nc pin page 60 - - - m30 vss - - - l33sdata[26]# pbpm32vss --- l35 scheck[2]# page 61 p b g m34 vss - - - l37sdata[28]# pbpm36vss --- n1picclk 0 pi- p2vss --- n3picd[0]# 0 pb- p4vss --- n5picd[1]# 0 pb- p6vss --- n7 key pin page 59 - - - p8 vss - - - n31 nc pin page 60 - - - p30 vcc_core - - - n33 sdata[25]# p b p p32 vcc_core - - - n35 sdata[27]# p b p p34 vcc_core - - - n37sdata[18]# pbgp36vcc_core --- q1 tck page 59 p i - r2 vcc_core - - - q3 tms page 59 p i - r4 vcc_core - - - q5 scanshiften page 61 p i - r6 vcc_core - - - q7 key pin page 59 - - - r8 vcc_core - - - q31 nc pin page 60 - - - r30 vss - - - q33sdata[24]# pbpr32vss --- q35sdata[17]# pbgr34vss --- q37sdata[16]# pbgr36vss --- s1 scanclk1 page 61 p i - t2 vss - - - s3 scaninteval page 61 p i - t4 vss - - - s5 scanclk2 page 61 p i - t6 vss - - - s7 nc pin page 60 - - - t8 vss - - - s31 nc pin page 60 - - - t30 vcc_core - - - s33 sdata[7]# p b g t32 vcc_core - - - table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
chapter 9 pin descriptions 53 23802e ? september 2000 amd duron ? processor data sheet preliminary information s35 sdata[15]# p b p t34 vcc_core - - - s37 sdata[6]# p b g t36 vcc_core - - - u1 tdi page 59 p i - v2 vcc_core - - - u3 trst# page 59 p i - v4 vcc_core - - - u5 tdo page 59 p o - v6 vcc_core - - - u7 nc pin page 60 - - - v8 vcc_core - - - u31 nc pin page 60 - - - v30 vss - - - u33 sdata[5]# p b g v32 vss - - - u35 sdata[4]# p b g v34 vss - - - u37 scheck[0]# page 61 p b g v36 vss - - - w1 fid[0] page 58 o - - x2 vss - - - w3 fid[1] page 58 o - - x4 vss - - - w5 vrefsys page 62 p - - x6 vss - - - w7 nc pin page 60 - - - x8 vss - - - w31 nc pin page 60 - - - x30 vcc_core - - - w33 sdatainclk[0]# p i g x32 vcc_core - - - w35 sdata[2]# p b g x34 vcc_core - - - w37 sdata[1]# p b p x36 vcc_core - - - y1 fid[2] page 58 o - - z2 vcc_core - - - y3 fid[3] page 58 o - - z4 vcc_core - - - y5 nc pin page 60 - - - z6 vcc_core - - - y7 key pin page 59 - - - z8 vcc_core - - - y31 nc pin page 60 - - - z30 vss - - - y33 scheck[1]# page 61 p b p z32 vss - - - y35 sdata[3]# p b g z34 vss - - - y37sdata[12]# pbp z36vss - - - aa1 dbrdy page 57 p o - ab2 vss - - - aa3 dbreq# page 57 p i - ab4 vss - - - aa5 sysvrefmode page 61 p i - ab6 vss - - - aa7 key pin page 59 - - - ab8 vss - - - aa31 nc pin page 60 - - - ab30 vcc_core - - - aa33 sdata[8]# p b p ab32 vcc_core - - - aa35 sdata[0]# p b g ab34 vcc_core - - - aa37sdata[13]# pbgab36vcc_core --- table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
54 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information ac1 stpclk# page 61 p i - ad2 vcc_core - - - ac3 plltest# page 60 p i - ad4 vcc_core - - - ac5 zn page 62 p - - ad6 vcc_core - - - ac7 vcc_z page 62 - - - ad8 nc pin page 60 - - - ac31 nc pin page 60 - - - ad30 nc pin page 60 - - - ac33 sdata[10]# p b p ad32 vss - - - ac35 sdata[14]# p b g ad34 vss - - - ac37 sdata[11]# p b g ad36 vss - - - ae1 a20m# page 57 p i - ae31 nc pin page 60 p - - ae3 pwrok page 60 p i - ae33 saddin[5]# p i g ae5 zp page 62 p - - ae35 sdataoutclk[0]# p o p ae7 vss_z page 62 - - - ae37 sdata[9]# - b g af2vss ---ag1ferr p age 58 - 0 - af4vss ---ag3reset# -i- af6 nc pin page 60 ---ag5nc pin p age 60 - - - af8 nc pin page 60 ---ag7key pin p age 59 - - - af10 nc pin page 60 ---ag9key pin p age 59 - - - af12 vss - - - ag11 corefb page 57 - - - af14 vcc_core - - - ag13 corefb# page 57 - - - af16 vss - - - ag15 key pin page 59 - - - af18 vcc_core - - - ag17 key pin page 59 - - - af20 vss - - - ag19 nc pin page 60 - - - af22 vcc_core - - - ag21 nc pin page 60 - - - af24 vss - - - ag23 nc pin page 60 - - - af26 vcc_core - - - ag25 nc pin page 60 - - - af28 nc pin page 60 - - - ag27 key pin page 59 - - - af30 nc pin page 60 - - - ag29 key pin page 59 - - - af32 nc pin page 60 - - - ag31 nc pin page 60 - - - af34 vcc_core - - - ag33 saddin[2]# p i g af36 vcc_core - - - ag35 saddin[11]# p i g ag37 saddin[7]# p i p ah2 vcc_core - - - aj1 ignne# page 59 p i - ah4 vcc_core - - - aj3 init# page 59 p i - ah6 amd pin page 57 - - - aj5 vcc_core - - - table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
chapter 9 pin descriptions 55 23802e ? september 2000 amd duron ? processor data sheet preliminary information ah8 nc pin page 60 - - - aj7 nc pin page 60 - - - ah10 vcc_core - - - aj9 nc pin page 60 - - - ah12 vss - - - aj11 nc pin page 60 - - - ah14 vcc_core - - - aj13 analog page 57 - - - ah16 vss - - - aj15 nc pin page 60 - - - ah18 vcc_core - - - aj17 nc pin page 60 - - - ah20 vss - - - aj19 nc pin page 60 - - - ah22 vcc_core - - - aj21 clkfwdrst page 57 p i p ah24 vss - - - aj23 vcca page 61 - - - ah26 vcc_core - - - aj25 pllbypass# page 60 p i - ah28 vss - - - aj27 nc pin page 60 - - - ah30 nc pin page 60 - - - aj29 nc pin - - - ah32 vss - - - aj31 sfillval# p i g ah34 vss - - - aj33 saddinclk# p i g ah36 vss - - - aj35 saddin[6]# p i p aj37 saddin[3]# p i g ak2 vss - - - al1 intr page 59 p i ak4 vss - - - al3 flush# page 59 p i ak6vss ---al5vcc_core --- ak8 nc pin page 60 - - - al7 nc pin page 60 - - - ak10 vcc_core - - - al9 nc pin page 60 - - - ak12 vss - - - al11 nc pin page 60 - - - ak14 vcc_core - - - al13 pllmon2 page 60 p i ak16 vss - - - al15 pllbypassclk# page 60 p i ak18 vcc_core - - - al17 clkin# page 57 p i p ak20 vss - - - al19 rstclk# page 57 p i p ak22 vcc_core - - - al21 k7clkout page 59 p o ak24 vss - - - al23 connect page 57 p i p ak26 vcc_core - - - al25 nc pin page 60 - - - ak28 vss - - - al27 nc pin page 60 - - - ak30 vcc_core - - - al29 saddin[1]# page 60 p i ak32 vss - - - al31 sdataoutval# p o p ak34 vcc_core - - - al33 saddin[8]# p i p ak36 vcc_core - - - al35 saddin[4]# p i g table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
56 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information al37 saddin[10]# p i g am2 vcc_core - - - an1 no pin page 60 - - - am4 vss - - - an3 nmi page 60 p i - am6 vss - - - an5 smi# page 61 p i - am8 nc pin page 60 - - - an7 nc pin page 60 - - - am10 vcc_core - - - an9 nc pin page 60 - - - am12 vss - - - an11 nc pin page 60 - i - am14 vcc_core - - - an13 pllmon1 page 60 0 b - am16 vss - - - an15 pllbypassclk page 60 i am18 vcc_core - - - an17 clkin page 57 i p am20 vss - - - an19 rstclk page 57 i p am22 vcc_core - - - an21 k7clkout# page 59 o am24 vss - - - an23 procrdy o p am26 vcc_core - - - an25 nc pin page 60 - - am28 vss - - - an27 nc pin page 60 - - am30 vcc_core - - - an29 saddin[12]# p i g am32 vss - - - an31 saddin[14]# p i g am34 vcc_core - - - an33 sdatainval# p i p am36 vss - - - an35 saddin[13]# p i g an37 saddin[9]# p i g table 19. socket a pin cross-reference by pin location (continued) pin name description l p r pin name description l p r
chapter 9 pin descriptions 57 23802e ? september 2000 amd duron ? processor data sheet preliminary information 9.3 detailed pin descriptions the information in this section pertains to table 19 on page 49. a20m# pin a20m# is an input from the system used to simulate address wrap-around in the 20-bit 8086. amd pin the motherboard should treat the amd pin (ah6) as an nc pin. a socket designer has the option of creating a top mold piece that blocks this pin location. however, sockets that populate the amd pin must be allowed, so the motherboard must always provide for a nc type pin at this pin location. amd socket a processors do not implement a pin at location ah6. when a socket that does not provide a pin hole at location ah6 is used, a non-amd pga370 part does not fit into socket a. amd system bus pins see the amd system bus specification , order# 21902 for information about the system bus pins ? procrdy, pwrok, reset#, saddin[14:2]#, saddinclk#, saddout[14:2]#, saddoutclk#, scheck[7:0]#, sdata[63:0]#, sdatainclk[3:0]#, sdatainval#, sdataoutclk[3:0]#, sdataoutval#, sfillval#. analog pin treat this pin as an nc. clkfwdrst pin clkfwdrst resets clock-forward circuitry for both the system and processor. clkin, rstclk (sysclk) pins connect clkin (an17) with rstclk (an19) and name it sysclk. connect clkin# (al17) with rstclk# (al19) and name it sysclk#. length match the clocks from the clock generator to the northbridge and processor. see ? sysclk and sysclk# pins ? on page 61 for more information. connect pin connect is an input from the system used for power management and clock-forward initialization at reset. corefb and corefb# pins corefb and corefb# are outputs to the system that provide amd duron processor core voltage feedback to the system. dbrdy and dbreq# pins dbrdy (aa1) and dbreq# (aa3) are routed to the debug connector. dbreq# is tied to vcc_core with a 1-kohm pullup.
58 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information ferr pin ferr is an output to the system that is asserted for any unmasked numerical exception independent of the ne bit in cr0. ferr is an open-drain active high signal that must be inverted and level shifted to an active low signal that is 3.3v when deasserted. for more information about ferr and ferr#, see the ? required circuits ? chapter of the motherboard pga design guide , order# 90009. fid[3:0] pins see ? frequency identification (fid[3:0]) ? on page 20 for the ac and dc characteristics for fid[3:0]. fid[3] (y3), fid[2] (y1), fid[1] (w3), and fid[0] (w1) are the 4-bit processor clock to sysclk ratio. table 20 describes the encodings of the clock multipliers on fid[3:0]. table 20. fid[3:0] clock multiplier encodings fid[3] fid[2] fid[1] fid[0] processor clock to sysclk frequency ratio 0000 11 0001 11.5 0010 12 0011 >= 12.5 0100 5 0101 5.5 0110 6 0111 6.5 1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 10.5 note: all ratios greater than or equal to 12.5x have the same fid[3:0] code of 0011, which causes the sip configuration for all ratios of 12.5x or greater to be the same.
chapter 9 pin descriptions 59 23802e ? september 2000 amd duron ? processor data sheet preliminary information the fid[3:0] signals are open-drain processor outputs that are pulled high on the motherboard and sampled by the northbridge at the deassertion of reset# to determine the sip (serialization initialization packet) that gets sent to the processor. see the amd system bus specification , order#21902 for more information about the sip and sip protocol. the processor fid[3:0] outputs are open drain and 2.5v tolerant. to prevent damage to the processor, if these signals are pulled high to above 2.5 v, they must be electrically isolated from the processor. for information about the fid[3:0] isolation circuit, see the motherboard pga design guide , order# 90009. flush# pin to the debug connector, this pin should be tied to vcc_core with a 1-kohm resistor, and to smi# with a 0-ohm resistor. the 0-ohm resistor is not populated. ignne# pin ignne# is an input from the system that tells the processor to ignore numeric errors. init# pin init# is an input from the system that resets the integer registers without affecting the floating-point registers or the internal caches. execution starts at 0ffff fff0h. intr pin intr is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. jtag pins tck (q1), tms (q3), tdi (u1), trst# (u3), and tdo (u5) are the jtag interface. connect these pins directly to the motherboard debug connector. pullup tdi, tck, tms, and trst# to vcc_core with 1-kohm resistors. k7clkout and k7clkout# pins k7clkout (al21) and k7clkout# (an21) are each run for 2 to 3 inches and then terminated with a resistor pair, 100 ohms to vcc_core and 100 ohms to vss. the effective termination resistance and voltage are 50 ohms and vcc_core/2. key pins these 16 locations are for processor type keying for forwards and backwards compatibility (g7, g9, g15, g17, g23, g25, n7, q7, y7, aa7, ag7, ag9, ag15, ag17, ag27, and ag29). motherboard designers should treat key pins like nc (no connect) pins. see ? nc pins ? on page 60 for more information. a socket designer has the option of creating a top mold piece
60 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information that allows pga key pins only where permitted. however, sockets that populate all key pins must be allowed, so the motherboard must always provide for pins at all key pin locations. nc pins the motherboard should provide a plated hole for an nc pin. the pin hole should not be electrically connected to anything. nmi pin nmi is an input from the system that causes a non-maskable interrupt. pga orientation pins no pin is present at pin locations a1 and an1 (see the processor socket 462 application note , order# 90020). motherboard designers should not allow for a pga socket pin at these locations. pll bypass and test pins plltest# (ac3), pllbypass# (aj25), pllmon1 (an13), pllmon2 (al13), pllbypassclk (an15), and pllbypassclk# (al15) are the pll bypass and test interface. this interface is tied disabled on the motherboard. all six pin signals are routed to the debug connector. all four processor inputs (plltest#, pllbypass#, pllmon1, and pllmon2) are tied to vcc_core with 1-kohm resistors. pwrok pin motherboard designs require power sequencing circuitry for processor pll startup protection. pll startup complications can occur if pwrok is asserted before the following voltages are valid: vcc_core pll voltage 3.3-v supply, which indicates the system clocks are stable. for more information, see the pwrok signal motherboard design application note , order# 90024 and the ? motherboard required circuits ? chapter of the motherboard pga design guide , order# 90009. saddin[1]# and saddout[1:0]# pins saddin[1]# is tied to vss with 1-kohm resistors, if this bit is not supported by the northbridge. saddout[1:0]# are nc, if these bits are not supported by the northbridge. for more information, see the amd system bus specification , order# 21902.
chapter 9 pin descriptions 61 23802e ? september 2000 amd duron ? processor data sheet preliminary information scan pins scanshiften (q5), scanclk1 (s1), scaninteval (s3), and scanclk2 (s5) are the scan interface. this interface is amd internal and is tied disabled with 1-kohm resistors to vss on the motherboard. scheck[7:0]# pin for systems that do not support ecc, scheck[7:0]# should be treated as nc pins. smi# pin smi# is an input that causes the processor to enter the system management mode. stpclk# pin stpclk# is an input that causes the processor to enter a lower power mode and issue a stop grant special cycle. sysclk and sysclk# pins sysclk and sysclk# are differential input clock signals provided to the processor ? s pll from a system-clock generator. see ? clkin, rstclk (sysclk) pins ? on page 57 for more information. sysvrefmode pin sysvrefmode (aa5) is low to ensure that the external vrefsys voltage is the actual voltage used by the input buffers and that no scaling occurs internally between the vrefsys voltage and the input threshold. this pin is tied low with a 1.0-kohm resistor. vcca pin vcca is the processor pll supply. vcca current ranges from 0 ma to 32 ma at ~1 ghz. vmax is 2.75 v and vmin is 2.25 v. decouple this pin with a 0.1-uf capacitor. for information about the vcca pin, see table 6, ? vcca ac and dc characteristics, ? on page 21 and the ? motherboard required circuits ? chapter of the motherboard pga design guide , order# 90009. vid[4:0] pins the vid[4:0] signals are outputs to the motherboard that indicate the required vcc_core voltage for the processor. the vcc_core id (vid) is sent to the motherboard vcc_core regulator. the processor vid[4:0] outputs are open drain and 2.5-v tolerant. to prevent damage to the processor, if these signals are pulled high to above 2.5 v, they must be electrically be isolated from the processor. see ? voltage identification (vid[4:0]) ? on page 20 for the ac and dc characteristics for vid[4:0]. the motherboard is required to pull vid[4:0] low for the voltage regulator to supply voltage in the appropriate range for
62 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information the amd duron processor. these voltage id values are defined intable 21. note: the vid[3:0] for slot a has a different code definition than vid[4:0] for socket a. for more information, see the ? required circuits ? chapter of the motherboard pga design guide , order# 90009. vrefsys pin vrefsys (w5) drives the threshold voltage for the system bus input receivers. vrefsys is set to 0.5 * vcc_core. in addition, to minimize vcc_core noise rejection from vrefsys, include decoupling capacitors. for more information, see the motherboard pga design guide , order# 90009. zn, vcc_z, zp, and vss_z pins zn (ac5), vcc_z (ac7), zp (ae5), and vss_z (ae7) are the push-pull compensation circuit pins. vcc_z is tied to vcc_core. vss_z is tied to vss. if push-pull mode is selected by the sip parameter syspushpull asserted (syspushpull=1), zn is tied to vcc_core with a table 21. vid[4:0] code to voltage definition vid[4:0] vcc_core (v) vid[4:0] vcc_core (v) 00000 1.850 10000 1.450 00001 1.825 10001 1.425 00010 1.800 10010 1.400 00011 1.775 10011 1.375 00100 1.750 10100 1.350 00101 1.725 10101 1.325 00110 1.700 10110 1.300 00111 1.675 10111 1.275 01000 1.650 11000 1.250 01001 1.625 11001 1.225 01010 1.600 11010 1.200 01011 1.575 11011 1.175 01100 1.550 11100 1.150 01101 1.525 11101 1.125 01110 1.500 11110 1.100 01111 1.475 11111 no cpu
chapter 9 pin descriptions 63 23802e ? september 2000 amd duron ? processor data sheet preliminary information resistor that has a resistance matching the impedance zo of the transmission line. zp is tied to vss with a resistor that has a resistance matching the impedance zo of the transmission line. if open-drain mode is selected by the sip parameter syspushpull deasserted (syspushpull=0), zn and zp should be resistively tied to either vcc_core or vss, but should not be left floating.
64 pin descriptions chapter 9 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
chapter 10 ordering information 65 23802e ? september 2000 amd duron ? processor data sheet preliminary information 10 ordering information standard amd duron ? processor products amd standard products are available in several operating ranges. the ordering part numbers (opn) are formed by a combination of the elements shown in figure 16. these opns are examples only. figure 16. pga opn example for the amd duron ? processor d 750 a s t 1 b note: spaces are added to the number shown above for viewing clarity only. pga opn max fsb: a = b = 200 mhz size of l2 cache: 1=64kbytes, 2=128kbytes case temperature: q=60 o c, x=65 o c, r = 70 c, y=75 o c, t=90 o c operating voltage: s = 1.5v, u = 1.6v, p = 1.7v, n = 1.8v package type: m = card module, a = pga speed: 600 mhz, 650 mhz, 700 mhz, 750 mhz, etc. family/architecture: d = amd duron ? processor architecture
66 ordering information chapter 10 amd duron ? processor data sheet 23802e ? september 2000 preliminary information
23802e ? september 2000 amd duron ? processor data sheet preliminary information appendix a conventions, abbreviations, and references 67 appendix a conventions, abbreviations, and references this section contains information about the conventions and abbreviations used in this document and a list of related publications. signals and bits n active-low signals ? signal names containing a pound sign, such as sfill#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. when used in this context, high and low are written with an initial upper case letter. n signal ranges ? in a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, d[63:0]). n reserved bits and signals ? signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. these bits and signals are reserved by amd for future implementations. when software reads registers with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. n three-state ? in timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels.
68 conventions, abbreviations, and references appendix a amd duron ? processor data sheet 23802e ? september 2000 preliminary information n invalid and don ? t-care ? in timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. data terminology the following list defines data terminology: n quantities ? a word is two bytes (16 bits) a doubleword is four bytes (32 bits) a quadword is eight bytes (64 bits) n addressing ? memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. n abbreviations ? the following notation is used for bits and bytes: kilo (k, as in 4-kbyte page) mega (m, as in 4 mbits/sec) giga (g, as in 4 gbytes of memory space) see table 23 for more abbreviations. n little-endian convention ? the byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left ? the little end is on the right and the big end is on the left. data structure diagrams in memory show low addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. n bit ranges ? in text, bit ranges are shown with a dash (for example, bits 9 ? 1). when accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, ad[31:0]). n bit values ? bits can either be set to 1 or cleared to 0. n hexadecimal and binary numbers ? unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b.
appendix a conventions, abbreviations, and references 69 23802e ? september 2000 amd duron ? processor data sheet preliminary information abbreviations and acronyms table 23 contains the definitions of abbreviations used in this document. table 22. abbreviations abbreviation meaning aampere f farad g giga- gbit gigabit gbyte gigabyte hhenry h hexadecimal k kilo- kbyte kilobyte m mega- mbit megabit mbyte megabyte mhz megahertz m milli- ms millisecond mw milliwatt micro- a microampere f microfarad h microhenry s microsecond v microvolt n nano- na nanoampere nf nanofarad nh nanohenry ns nanosecond ohm ohm ppico- pa picoampere
70 conventions, abbreviations, and references appendix a amd duron ? processor data sheet 23802e ? september 2000 preliminary information table 23 contains the definitions of acronyms used in this document. pf picofarad ph picohenry ps picosecond s second vvolt wwatt table 23. acronyms abbreviation meaning acpi advanced configuration and power interface agp accelerated graphics port apci agp peripheral component interconnect api application programming interface apic advanced programmable interrupt controller bios basic input/output system bist built-in self-test biu bus interface unit ddr double-data rate dimm dual inline memory module dma direct memory access dram direct random access memory ecc error correcting code eide enhanced integrated device electronics eisa extended industry standard architecture eprom enhanced programmable read only memory ev6 digital ? alpha ? bus fifo first in, first out gart graphics address remapping table hstl high-speed transistor logic ide integrated device electronics isa industry standard architecture table 22. abbreviations (continued) abbreviation meaning
appendix a conventions, abbreviations, and references 71 23802e ? september 2000 amd duron ? processor data sheet preliminary information jedec joint electron device engineering council jtag joint test action group lan large area network lru least-recently used lvttl low voltage transistor transistor logic msb most significant bit mtrr memory type and range registers mux multiplexer nmi non-maskable interrupt od open drain pbga plastic ball grid array pa physical address pci peripheral component interconnect pde page directory entry pdt page directory table pll phase locked loop pmsm power management state machine pos power-on suspend post power-on self-test ram random access memory rom read only memory rxa read acknowledge queue sdi system dram interface sdram synchronous direct random access memory sip serial initialization packet smbus system management bus spd serial presence detect sram synchronous random access memory srom serial read only memory tlb translation lookaside buffer tom top of memory ttl transistor transistor logic vas virtual address space vpa virtual page address table 23. acronyms (continued) abbreviation meaning
72 conventions, abbreviations, and references appendix a amd duron ? processor data sheet 23802e ? september 2000 preliminary information vga video graphics adapter usb universal serial bus zdb zero delay buffer table 23. acronyms (continued) abbreviation meaning

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